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US 2026/0156929 A1Published application
Group iii-v power semiconductor device and method of manufacturing same
AssigneeDB HiTek Co., Ltd.
InventorsMin Su CHO, Jong Hyun LEE, Woo Chul JEON, Ji Houn JUNG, Ung Bi SON, Jun Hyeok LEE, Dong Hyeok SON
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Abstract
Proposed are a group III-V power semiconductor device and a method of manufacturing the same. More particularly, proposed are a group III-V power semiconductor device in which regions that differ from each other in threshold voltage characteristics are implemented on a single wafer, and to a method of manufacturing the same.
Claims20
A group III-V power semiconductor device comprising:
- a first region;
- a second region having a threshold voltage that differs from that of the first region;
- a substrate in the first and second regions;
- a channel layer on the substrate in the first and second regions;
- a barrier layer on the channel layer in the first and second regions;
- a capping layer on the barrier layer in the first region;
- a first gate electrode on the capping layer;
- a deactivated region on the barrier layer in the second region;
- and
- a second gate electrode on the deactivated region.
7 more elements
A group III-V power semiconductor device comprising:
- a first region;
- a second region having a threshold voltage that differs from that of the first region;
- a substrate in the first and second regions;
- a channel layer on the substrate in the first and second regions;
- a barrier layer on the channel layer in the first and second regions;
- a first capping layer on the barrier layer in the first region;
- a first gate electrode on the first capping layer;
- a second capping layer on the barrier layer in the second region;
- a deactivated region in the second capping layer;
- and
- a second gate electrode on the deactivated region.
8 more elements
A method of manufacturing a group III-V power semiconductor device, the method comprising:
- sequentially forming a buffer layer, a channel layer, and a barrier layer on a substrate in a first region and a second region;
- forming a first capping layer in the first region and a deactivated region in a second capping layer of the second region;
- and
- forming a first gate electrode on the first capping layer and a second gate electrode on the deactivated region.
1 more element
Dependencies are inferred from the claim text.