Transistor structure and manufacturing method thereof

Abstract

Provided are a transistor structure and a manufacturing method thereof. The transistor structure includes a gate dielectric layer, a gate disposed on the gate dielectric layer, a spacer structure located on the gate dielectric layer and disposed on the sidewall of the gate, first, second and third doped regions, and a metal silicide layer. The first doped regions are disposed in the substrate on two sides of the gate. The second doped regions are disposed in the first doped regions, respectively. The third doped regions is disposed in the second doped regions, respectively. The metal silicide layer is disposed at the surface of the third doped regions. In the channel direction, the first doped regions extend below the gate to partially overlap with the gate, the second doped regions extends below the spacer structure, and the metal silicide layer does not extend below the gate.

Dependencies are inferred from the claim text.