System and method for low density parity check (ldpc) code with 1/2 code rate
AssigneeAvago Technologies International Sales Pte. Limited
InventorsRethnakaran Pulikkoonattu, Andrew Blanksby, Vinko Erceg
Life of this patent
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Abstract
In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1/2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 288 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.
Claims20
A method, comprising:
- identifying, by baseband circuitry of a first device according to a code rate of 1/2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code, the first binary parity check matrix corresponding to a first exponent matrix having 288 values;
- encoding, by an encoder of the baseband circuitry of the first device, data using the first binary parity check matrix;
- and
- transmitting, by a transmitter of the first device, the encoded data over a channel,
- wherein the first exponent matrix comprises the following values:
- [115 −1 −1 −1 101 −1 23 −1 100 −1 158 −120 −1 −1 −1 −1 −1 −1 −16 −157 −1 −1 −1 −1 −1 110 15 −1 −1 −1 0 0 −1 −1 −1 −1 −1 −1 −1 −1 −1 60 −1 −1 −1 49 74 −1 −1 112 29 −1 −1 −1 −1 0 0 −1 −1 −1 −1 −1 −1 −1 −1 124 106 −1 −1 107 −1 −1 6 70 −1 −1 −1 −1 −1 −1 0 0 −1 −1 −1 −1 −1 −1 −1 81 −1 −1 40 133 −1 −1 45 57 −1 −1 −1 −1 −1 −1 −1 0 0 −1 −1 −1 −1 −1 −1 0 −1 −1 −1 17 −1 84 −1 101 −1 −1 17 −1 −1 −1 −1 −1 0 0 −1 −1 −1 −1 −1 139 158 159 −1 −1 −1 112 −1 105 −1 −1 −−1 0 −1 −1 −1 −1 −1 0 0 −1 −1 −1 −1 131 −1 −1 −1 77 114 −1 −1 145 −1 55 −1 −1 −1 −1 −1 −1 −1 −1 0 0 −1 −1 −1 129 −1 −1 −1 28 105 −1 −1 61 −1 −1 65 −1 −1 −1 −1 −1 −1 −1 −1 0 0 −1 −1 −1 90 −1 141 1 −1 −1 −1 155 18 −1 −1 −1 −1 −1 −1 −1 −1 −1 −1 −1 0 0 −1 4 112 −1 135 70 −1 −1 −1 −1 −1 25 −1 −1 −1 −1 −1 −1 −1 −1 −1 −1 −1 0 0 49 −1 123 −1 121 −1 −1 54 102 −1 −1 32 2 −1 −1 −1 −1 −1 −1 −1 −1 −1 −1 0].
An apparatus comprising:
- a transmitter and baseband circuitry, wherein the baseband circuitry is configured to:
- identify, according to a code rate of 1/2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code, the first binary parity check matrix corresponding to a first exponent matrix having 288 values;
- generate the first exponent matrix by selecting at least 286 values from a second exponent matrix having the same dimensions as dimensions of the first exponent matrix by shifting one or two values of the first exponent matrix from one or more corresponding positive values of the second exponent matrix by −1 or +1;
- encode, by an encoder of the baseband circuitry, data using the first binary parity check matrix;
- and
- transmit, by the transmitter, the encoded data over a channel.
An apparatus comprising:
- a receiver configured to receive encoded data;
- and
- baseband circuitry configured to:
- identify, according to a code rate of 1/2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code, the first binary parity check matrix corresponding to a first exponent matrix having 288 values;
- and
- decode, by a decoder of the baseband circuitry, the received encoded data using the first binary parity check matrix, wherein
- the first exponent matrix comprises at least 286 values selected from a second exponent matrix having the same dimensions as dimensions of the first exponent matrix, and
- the first exponent matrix comprises one or two values shifted from one or more corresponding positive values of the second exponent matrix by −1 or +1.
Dependencies are inferred from the claim text.