Asymmetric hard read channel estimation in memory devices

A system for improving a performance of a decoder in a memory device, comprising:

• one or more processors and a memory including instructions stored thereupon, wherein the instructions upon execution by the one or more processors cause the one or more processors to:
• receive a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code;
• determine, based on the noisy codeword, a ones count and a checksum;
• determine, based on the ones count and the checksum, an asymmetric ratio, a first log-likelihood ratio (LLR) value indicative of a bit being zero-valued, and a second LLR value indicative of the bit being one-valued;
• generate an LLR sequence by applying the first LLR value and the second LLR value to each element of the noisy codeword;
• and
• perform a hard decoding operation on the LLR sequence to generate a candidate version of the transmitted codeword.

A non-transitory computer-readable storage medium having instructions stored thereupon for improving a performance of a decoder in a memory device, comprising:

• instructions for receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code;
• instructions for determining, based on the noisy codeword, a ones count and a checksum;
• instructions for determining, based on the ones count and the checksum, an asymmetric ratio, a first log-likelihood ratio (LLR) value indicative of a bit being zero-valued, and a second LLR value indicative of the bit being one-valued;
• instructions for generating an LLR sequence by applying the first LLR value and the second LLR value to each element of the noisy codeword;
• and
• instructions for performing a hard decoding operation on the LLR sequence to generate a candidate version of the transmitted codeword.