System and method for low density parity check (ldpc) code with 3/4 code rate
AssigneeAvago Technologies International Sales Pte. Limited
InventorsRethnakaran Pulikkoonattu, Andrew Blanksby, Vinko Erceg
Life of this patent
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Abstract
In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3/4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.
Claims20
An apparatus comprising:
- a baseband circuitry configured to:
- identify, according to a code rate of 3/4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code, the first binary parity check matrix corresponding to a first exponent matrix having 144 values;
- generate the first exponent matrix by selecting at least 142 values from a second exponent matrix having the same dimensions as dimensions of the first exponent matrix by shifting one or two values of the first exponent matrix from one or more corresponding positive values of the second exponent matrix by −1 or +1;
- encode, using an encoder of the baseband circuitry, data using the first binary parity check matrix;
- and
- transmit, using a transmitter, the encoded data over a channel.
An apparatus comprising:
- baseband circuitry configured to:
- identify, according to a code rate of 3/4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code, the first binary parity check matrix corresponding to a first exponent matrix having 144 values;
- and
- decode, using a decoder of the baseband circuitry, encoded data received by a receiver using the first binary parity check matrix,
- wherein the first exponent matrix comprises the following values:
- [96 59 56 78 18 122 −1 −1 −1 126 90 161 −1 −1 −1 74 65 45 2 0 −1 −1 −1 −1 8 98 85 97 22 61 −1 −1 −1 98 35 82 74 31 −1 108 −1 −1 −1 0 0 −1 −1 −1 71 153 156 102 74 70 42 −1 35 128 −1 −1 −1 118 14 −1 −1 65 −1 −1 0 0 −1 −1 18 131 88 18 109 113 146 69 84 −1 −1 −1 71 −1 −1 −1 92 79 0 −1 −1 0 0 −1 7 124 15 161 137 53 −1 161 110 −1 72 −1 53 −1 18 −1 145 −1 −1 −1 −1 −1 0 0 53 151 66 42 138 118 6 77 −1 −1 −1 70 −1 125 72 53 −1 −1 2 −1 −1 −1 −1 0].
A non-transitory computer readable medium storing program instructions for causing one or more processors to:
- identify, according to a code rate of 3/4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code, the first binary parity check matrix corresponding to a first exponent matrix having 144 values;
- encode, by an encoder, data using the first binary parity check matrix;
- and
- transmit, by a transmitter, the encoded data over a channel,
- wherein the first exponent matrix comprises the following values:
- [96 59 56 78 18 122 −1 −1 −1 126 90 161 −1 −1 −1 74 65 45 2 0 −1 −1 −1 −1 8 98 85 97 22 61 −1 −1 −1 98 35 82 74 31 −1 108 −1 −1 −1 0 0 −1 −1 −1 71 153 156 102 74 70 42 −1 35 128 −1 −1 −1 118 14 −1 −1 65 −1 −1 0 0 −1 −1 18 131 88 18 109 113 146 69 84 −1 −1 −1 71 −1 −1 −1 92 79 0 −1 −1 0 0 −1 7 124 15 161 137 53 −1 161 110 −1 72 −1 53 −1 18 −1 145 −1 −1 −1 −1 −1 0 0 53 151 66 42 138 118 6 77 −1 −1 −1 70 −1 125 72 53 −1 −1 2 −1 −1 −1 −1 0].
Dependencies are inferred from the claim text.