Clock and data recovery circuit suitable for high-speed serdes and recovery method

A clock and data recovery circuit suitable for high-speed SerDes, comprising:

• an analog front end, which inputs a receiving signal and outputs a result of a phase detector;
• a phase discrimination accumulator, which is used for accumulating the result of the phase detector;
• a gain control unit, which is used for adjusting a gain of a trunk signal;
• a first branch, which comprises a proportion voter and a phase gain unit;
• a second branch, which comprises a weight voter and a frequency integration unit;
• an adder, which is used for adding output results of the phase gain unit and the frequency integration unit, wherein an output of the adder sequentially passes through a phase accumulator and a phase interpolator;
• and
• the phase interpolator, which is used for outputting a sampling clock for the analog front end to use;
• wherein, the weight voter is used for linear amplification when an absolute value of an accumulative value of phase discrimination exceeds a weight limit value, no adjustment is made when the absolute value of the accumulative value of phase discrimination does not exceed the weight limit value, and the weight voter is expressed as follows:
• Kv
• ⁢
• 2
• =
• {
• 0
• ,
• ❘
• "\[LeftBracketingBar]"
• pd
• ❘
• "\[RightBracketingBar]"
• <
• α
• γ
• ,
• ❘
• "\[LeftBracketingBar]"
• pd
• ❘
• "\[RightBracketingBar]"
• ≥
• α
• (
• 1
• )
• wherein, γ is a gain coefficient of the weight voter, α is the set weight limit value, pd is the accumulative value of phase discrimination, and Kv2 is an output of the weight voter;
• and
• the proportion voter is used for linear amplification under any accumulative value of phase discrimination, and the proportion voter is expressed as follows:
• Kv
• ⁢
• 1
• =
• β
• (
• 2
• )
• wherein, β is a gain coefficient of the proportion voter, and Kv1 is an output of the proportion voter.