Ferroelectric fet based contest-switching fpga enabling dynamic reconfiguration for adaptive deep learning machines

Abstract

Embodiments can relate to a field-programmable gate array having a platform including an interconnect network of configuration blocks. The configuration blocks can include one or more configurable logic blocks (CLBs), one or more connection blocks (CBs), and one or more switch blocks (SBs). Each CLB can include a look-up table (LUT) cell configured to perform a logic operation. Each CB can be configured to connect one or more CLBs to the interconnection network. Each SB can be configured to connect routes between the configuration blocks. One or more or the CBs can include a 1FeFET for a single configuration, one or more of the CBs can include a 2T-2FeFET for a multiple configuration, one or more of the CLBs can include a 1FeFET LUT cell for a single configuration, or one or more of the CLBs can include two 1FeFET LUT cells for a multiple configuration.

Dependencies are inferred from the claim text.