Glitch rejection for fsk demodulation

A system for high bitrate frequency-shift keying (FSK) demodulation, the system comprising:

• a glitch rejection circuit configured to receive an input signal from a zero-crossing comparator and generate a glitch-free output, the glitch rejection circuit comprising:
• a first stage averaging circuit with a programmable length,
• a second stage averaging circuit coupled to an output of the first stage averaging circuit, and
• a hysteresis comparator with programmable high and low thresholds;
• a conditioning circuit configured to perform a blanking operation, perform a filtering operation, or be bypassed in response to the operational mode of the conditioning circuit;
• and
• an FSK demodulator circuit configured to receive the glitch-free output from the glitch rejection circuit.

A method for glitch rejection in a frequency-shift keying (FSK) demodulator, the method comprising:

• receiving a binary input signal sampled at a system frequency;
• processing the binary input signal through a first stage averaging circuit with a programmable length;
• processing an output of the first stage averaging circuit through a second stage averaging circuit;
• applying a hysteresis comparator to an output of the second stage averaging circuit;
• and
• outputting a glitch-free clock signal for use by a counter in the FSK demodulator.