Attenuator with passgate

A method comprising:

• providing a first input signal to a first current terminal of a first passgate and providing a second input signal to a first current terminal of a second passgate, the first input signal and the second input signal are differential signals to each other, the first passgate includes a first transistor and a second transistor, the first transistor being of a first conductivity type and the second transistor being a second conductivity type opposite the first conductivity type, the second passgate includes a third transistor and a fourth transistor, the third transistor being of the first conductivity type and the second transistor being of the second conductivity type;
• controlling a control terminal voltage of the first transistor with an output of a first source follower, an input of the first source follower receives the second input signal;
• controlling a control terminal voltage of the second transistor with an output of a second source follower, an input of the second source follower receives the first input signal;
• controlling a control terminal voltage of the third transistor with an output of a third source follower, an input of the third source follower receives the first input signal;
• controlling a control terminal voltage of the fourth transistor with an output of a fourth source follower, an input of the fourth source follower receives the second input signal;
• providing a first output signal at a second current terminal of the first passgate and providing a second output signal at a second current terminal of the second passgate, wherein the first output signal and the second output signal are differential signals to each other.

A circuit, comprising:

• a first input terminal, configured to receive a first input signal;
• a second input terminal, configured to receive a second input signal, wherein the first input signal and the second input signal are differential signals to each other;
• a first output terminal configured to provide a first output signal;
• a second output terminal configured to provide a second output signal, wherein the first output signal and the second output signal are differential signals to each other;
• a first passgate including a first transistor of a first conductivity type and a second transistor of a second conductivity type coupled in parallel with the first transistor, wherein a first current terminal of the first transistor and a first current terminal of the second transistor are coupled together and are coupled to the first input terminal to receive the first input signal, wherein a second current terminal of the first transistor and a second current terminal of the second transistor are coupled together and coupled to the first output terminal to provide the first output signal;
• a first source follower including an output coupled to a control terminal of the second transistor and including an input coupled to the first input terminal to receive the first input signal;
• a second source follower including an output coupled to the control terminal of the first transistor and including an input coupled to the second input terminal to receive the second input signal;
• a second passgate including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type coupled in parallel with the third transistor, wherein a first current terminal of the third transistor and a first current terminal of the fourth transistor are coupled together and are coupled to the second input terminal to receive the second input signal (INN), wherein a second current terminal of the third transistor and a second current terminal of the fourth transistor are coupled together and coupled to the second output terminal to provide the second output signal;
• a third source follower including an output coupled to a control terminal of the fourth transistor and including an input coupled to the second input terminal to receive the second input signal;
• a fourth source follower including an output coupled to the control terminal of the third transistor and including an input coupled to the first input terminal to receive the first input signal.