Clock modulation circuit and clock modulation method
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorsShinji HIROKAWA, Tetsuya NAKAMURA
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Abstract
According to one embodiment, a clock modulation circuit includes a clock output circuit that outputs a clock signal and a multi-divider circuit that has a plurality of frequency division circuits to which the clock signal from the clock output circuit is input. Each frequency division circuit is configured to frequency divide the clock signal. A frequency division control circuit is configured to control a frequency division start time for each of the frequency division circuits and control a phase difference between output signals of at least one pair of frequency division circuits in the plurality of frequency division circuits based on a period of the clock signal.
Claims20
A clock modulation circuit, comprising:
- a clock output circuit configured to output a clock signal;
- a multi-divider circuit that has a plurality of frequency division circuits to which the clock signal from the clock output circuit is input, each frequency division circuit being configured to frequency divide the clock signal;
- and
- a frequency division control circuit configured to control a frequency division start time for each of the frequency division circuits and control a phase difference between output signals of at least one pair of frequency division circuits in the plurality of frequency division circuits based on a period of the clock signal.
A clock modulation circuit, comprising:
- a clock output circuit configured to output a clock signal;
- a multi-divider circuit to which the clock signal is input from the clock output circuit, the multi-divider circuit having a first frequency division circuit and a second frequency division circuit, each of which being configured to perform frequency division on the clock signal;
- and
- a frequency division control circuit configured to transmit a first frequency division start signal to the first frequency division circuit and a second frequency division start signal to the second frequency division circuit.
A clock modulation method for a clock modulation circuit, the method comprising:
- transmitting a first frequency division start signal from a frequency division control circuit to a first frequency division circuit that frequency divides a clock signal;
- outputting a first output signal from the first frequency division circuit, the first output signal being a frequency divided clock signal;
- transmitting a second frequency division start signal from the frequency division control circuit to a second frequency division circuit that frequency divides the clock signal;
- and
- outputting a second output signal from the second frequency division circuit, the second output signal being a frequency divided clock signal.
Dependencies are inferred from the claim text.