Class ab quiescent current optimization

Abstract

Embodiments of the present disclosure provide techniques for optimizing quiescent current in an amplifier. The amplifier may include an output stage associated with a quiescent current; a set of NMOS transistors comprising a first NMOS transistor and a second NMOS transistor connected together. The first NMOS transistor may have a first bias current. The amplifier may further include a first set of PMOS transistors comprising a first PMOS transistor and a second PMOS transistor. The first PMOS transistor may have a second bias current. The amplifier may further include an optimization circuit. The optimization circuit may include a current steering circuit that is driven by a threshold current. The optimization circuit may further include a level shifting device connected to the current steering circuit. The current steering circuit may be configured to adjust the first bias current based on the threshold current.

Dependencies are inferred from the claim text.