Systems, methods, and media for computer processing that leverages cache line invalidation and cryptography at the cache coherency level

A method for computer processing that leverages cache line invalidation and data cryptography at the cache coherency level, the method comprising:

• maintaining, by a cache coherent interconnect, cache coherency between a plurality of caches coupled to a processor;
• receiving, by a hardware agent coupled to the cache coherent interconnect and acting as a coherent managers, a snoop request for an instruction cache line for a current cache block, wherein the instruction cache line is stored in the memory as encrypted data and the snoop request is based on an original request initiated at the processor;
• transmitting, from the hardware agent and to the cache coherent interconnect, a snoop response indicating that the hardware agent stores the instruction cache line for the current cache block;
• obtaining, by the hardware agent, the encrypted data from a memory;
• decrypting, by the hardware agent using a key stored at the hardware agent, the encrypted data to generate a decrypted instruction cache line;
• transmitting, by the hardware agent, the decrypted instruction cache line to the processor by way of the cache coherent interconnect and plurality of caches, wherein the decrypted instruction cache line includes an invalidate instruction for the current cache block followed by a branch instruction for the current cache block.

A system for computer data cryptography at the cache coherency level, the system comprising:

• a memory;
• a processor coupled to a plurality of caches;
• a cache coherent interconnect connected to the processor and the memory, the cache coherent interconnect configured to maintain coherency between the plurality of caches;
• and
• a hardware agent coupled to the cache coherent interconnect as a coherent manager, the hardware agent configured to:
• receives a snoop request for requested data from the cache coherent interconnect, wherein the requested data is stored at a physical address of the memory that is being monitored by the hardware agent and the requested data is stored as encrypted data at the physical address;
• transmit, to the cache coherent interconnect, a snoop response indicating that the hardware agent stores the requested data even though the hardware agent does not store the data;
• obtain the encrypted data from the physical address of the memory;
• decrypt, using a key stored at the hardware agent, the encrypted data to generate decrypted data;
• and
• transmit the decrypted data to the processor by way of the cache coherent interconnect and plurality of caches, wherein the decrypted data is returned to the processor as one or more cache lines and the one or more cache lines are invalidated in the plurality of caches before the hardware agent provides next decrypted data to the processor in the form of one or more other cache lines.