Control/data architecture for very high throughput computing
AssigneeKinzinger Automation GmbH
InventorKlaus Kinzinger
Life of this patent
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Abstract
A control/data processor architecture is disclosed which merges data flow with control-flow into a unified control/data flow, enabling thread-level program execution—traditionally bound to a single-core hardware context—to transcend thread, task, and processor boundaries. The architecture supports software-pipelining of entire high-performance computing (HPC) kernels of arbitrary size and complexity, achieving high throughput and instruction-level parallelism. Additionally, the architecture accelerates sparse artificial intelligence workloads with very high sustained throughput and performance per watt.
Claims9
A programmable data processing apparatus comprising:
- a combined data-processing and storage unit (DPSU) comprising at least one arithmetic logic unit and at least one memory system, the DPSU being configured to execute a set of data-transforming and data-transport operations specified by an instruction-set architecture (ISA) of the apparatus, the set comprising at least one of arithmetic, logic, or other foundational data-transforming operations, and at least one of data load, store, transfer, or other foundational data-transport operations, the data-transforming and data-transport operations of the set operating on data of a set of data types supported by the apparatus as per the ISA, and wherein at least one part of a memory of the DPSU comprises a tagged memory that is configured to operate as at least a random-access memory system providing at least one memory-address space accessible through the ISA;
- and
- a programmable control unit (CU) configured to execute further operations specified by the ISA, the further operations comprising at least one of instruction-fetch, decode, issue, dispatch, or branch, the CU being configured, in at least one operational mode of the apparatus and under control of code fetched from the DPSU, to fetch at least one operand from the tagged memory, the operand comprising at least one operand data word and at least one associated operand tag word, and to control the DPSU by specifying at least one operation of the set of data-transforming and data-transport operations to be executed on the operand;
- characterized in that
- the CU is configured, in at least one operational mode of the apparatus, to interpret information comprised in the at least one operand tag word as execution-control information that affects execution behavior of the operation, including at least one of:
- (i) information indicating whether the operand data word is valid and the operation is enabled for regular execution, or the operand data word is idle, in which case execution of the operation may be skipped, altered, redirected, or replaced;
- (ii) information defining an execution-control context for the operation, for example a request for loop termination;
- or
- (iii) information indicating whether the operand data word is to be interpreted, at least in part, as execution-control information for the CU.
Dependencies are inferred from the claim text.