Method and apparatus with scalar-to-vector binary instruction translation

A computing device comprising:

• one or more processors;
• and
• memory storing instructions configured to cause the one or more processors to:
• receive and decode an instruction stream comprising instructions and pieces of instruction-information respectively corresponding to the instructions;
• determine whether the instructions in the instruction stream are translatable into a vector instruction stream based on the pieces of instruction-information;
• and
• based on a result of the determining, translate the instructions of the instruction stream to a vector instruction stream, the translating comprising translating at least some of the instructions of the instruction stream to vector instructions in a vector-specific instruction set by replacing scalar instructions of a first instruction set architecture (ISA) with functionally equivalent vector instructions of a vector-specific ISA.