Apparatus, system, and method of compiling code for a processor
AssigneeMobileye Vision Technologies Ltd.
InventorsMichael MARJIEH, Alon KOM, Oren BENITA BEN-SIMHON
Life of this patent
Estimating the term…
Abstract
For example, a compiler may be configured to compile a source code into a target code configured for execution by a target processor in a plurality of execution cycles including a first execution cycle, a second execution cycle after the first execution cycle, and a third execution cycle after the second execution cycle. For example, the target code may include one or more no operation (no-op) instructions configured to maintain a first variable live such that a value of the first variable is to be available in a register of the target processor at the first execution cycle and at the third execution cycle.
Claims24
-27. (canceled)
A product comprising one or more tangible computer-readable non-transitory storage media comprising computer-executable instructions operable to, when executed by at least one processor, enable the at least one processor to cause a compiler to:
- compile a source code into a target code, the target code configured for execution by a target processor in a plurality of execution cycles comprising a first execution cycle, a second execution cycle after the first execution cycle, and a third execution cycle after the second execution cycle, wherein the target code comprises one or more no operation (no-op) instructions configured to maintain a first variable live such that a value of the first variable is to be available in a register of the target processor at the first execution cycle and at the third execution cycle, wherein the target code comprises a first instruction to be applied to the value of the first variable in the register at the first execution cycle, a second instruction to be applied to a value of a second variable in the register at the second execution cycle, and a third instruction to be applied to the value of the first variable in the register at the third execution cycle;
- and
- output the target code.
A computing system comprising:
- at least one memory to store instructions;
- and
- at least one processor to retrieve the instructions from the memory and to execute the instructions to cause the computing system to:
- compile a source code into a target code, the target code configured for execution by a target processor in a plurality of execution cycles comprising a first execution cycle, a second execution cycle after the first execution cycle, and a third execution cycle after the second execution cycle, wherein the target code comprises one or more no operation (no-op) instructions configured to maintain a first variable live such that a value of the first variable is to be available in a register of the target processor at the first execution cycle and at the third execution cycle, wherein the target code comprises a first instruction to be applied to the value of the first variable in the register at the first execution cycle, a second instruction to be applied to a value of a second variable in the register at the second execution cycle, and a third instruction to be applied to the value of the first variable in the register at the third execution cycle;
- and
- output the target code.
A method comprising:
- compiling a source code into a target code, the target code configured for execution by a target processor in a plurality of execution cycles comprising a first execution cycle, a second execution cycle after the first execution cycle, and a third execution cycle after the second execution cycle, wherein the target code comprises one or more no operation (no-op) instructions configured to maintain a first variable live such that a value of the first variable is to be available in a register of the target processor at the first execution cycle and at the third execution cycle, wherein the target code comprises a first instruction to be applied to the value of the first variable in the register at the first execution cycle, a second instruction to be applied to a value of a second variable in the register at the second execution cycle, and a third instruction to be applied to the value of the first variable in the register at the third execution cycle;
- and
- outputting the target code.
Dependencies are inferred from the claim text.