Current mirror, gate driver and method for controlling an output current

The current mirror circuit of any one of the preceding claims, wherein the matching circuitry comprises:

• a third transistor having a control terminal, a first current terminal coupled to the control terminal of the third transistor, and a second current terminal;
• a fourth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal, and a second current terminal;
• a second current source configured to control a second reference current between the first and second current terminals of the third transistor;
• and
• a third current source configured to control a third reference current between the first and second current terminals of the fourth transistor.
• wherein said input of said matching circuitry is coupled to the second current terminal of the third transistor;
• wherein said output of said matching circuitry is coupled to the second current terminal of the fourth transistor.

The current mirror circuit of any one of the preceding claims, further comprising one of the following features:

• (i) wherein the first transistor and the second transistor are NMOS transistors, and the third transistor and the fourth transistor are PMOS transistors;
• (ii) wherein the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors;
• (iii) wherein the first transistor and the second transistor are NPN transistors, and the third transistor and the fourth transistor are PNP transistors;
• (iv) wherein the first transistor and the second transistor are PNP transistors, and the third transistor and the fourth transistor are NPN transistors.

A method for controlling an output current, the method comprising:

• providing a first reference current between the first and second current terminals of a first transistor;
• generating an output current between the first and second current terminals of a second transistor, the control terminal of the second transistor being coupled to the control terminal of the first transistor;
• and
• providing, at the first current terminal of the first transistor, a voltage corresponding to a voltage at the first current terminal of the second transistor.