System on chip and debugging method for system on chip

A system on chip, comprising:

• a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronization circuits connected by a scan-chain;
• a power management unit configured to control power gating for the plurality of blocks;
• a clock management unit configured to control a clock signal provided to the plurality of blocks;
• and
• a test access port (TAP) controller configured to control an operation of the plurality of blocks based on a test data in (TDI) signal synchronized with a test clock (TCK) signal and a test mode select (TMS) signal, and including a first register configured to store a first data for controlling the power management unit and the clock management unit, wherein
• the TAP controller is configured to generate a first control signal, the first control signal being configured to control the power management unit and the clock management unit based on the TMS signal and the first data,
• the power management unit is configured to turn on power to the plurality of blocks based on the first control signal, and
• the clock management unit is configured to stop the clock signal provided to the plurality of blocks based on the first control signal.

A debugging method for a system on chip comprising a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronization circuits connected by a scan-chain, the debugging method comprising:

• receiving, by a test access port (TAP) controller, a debugging request signal;
• transmitting, by the TAP controller, a first control signal generated based on a test mode selection (TMS) signal and a first data to a power management unit and a clock management unit based on the debugging request signal;
• turning on power provided to the plurality of blocks based on the first control signal by the power management unit;
• and
• stopping all clock signals provided to the plurality of blocks based on the first control signal by the clock management unit,
• wherein the TAP controller includes a first register that stores first data for controlling the power management unit and the clock management unit.