Stacking and Racking Semiconductor Chips Glass or Ceramic Circuits
AssigneeSciperio, Inc
InventorKenneth H. Church
Life of this patent
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Abstract
A microelectronics device includes a plurality of chips, a plurality of interconnect layers, each of the at least one interconnect layers comprised of one of glass and ceramic with circuitry patterned thereon. Each of the plurality of interconnect layers is operatively connected to neighboring ones of the plurality of chips and the plurality of interconnect layers using nanoparticle ink or paste to provide for electrical and mechanical bonding. At least one of the plurality of interconnect layers may have a surface extending across surfaces of multiple chips within the plurality of chips. The circuitry may include traces and vias to interconnect pads for I/O, ground, and power signals throughout the microelectronics device.
Claims21
A microelectronics device, comprising:
- a plurality of chips;
- a plurality of interconnect layers, each of the at least one interconnect layers comprised of one of glass and ceramic with circuitry patterned thereon;
- wherein the circuitry comprises traces and vias to interconnect pads for I/O, ground, and power signals throughout the microelectronics device;
- wherein each of the plurality of interconnect layers is operatively connected to neighboring ones of the plurality of chips and the plurality of interconnect layers using nanoparticle ink or paste to provide for electrical and mechanical bonding.
A microelectronics device, comprising:
- a plurality of chips;
- a plurality of interconnect layers, each of the at least one interconnect layers comprised of one of glass and ceramic with circuitry patterned thereon;
- wherein the circuitry comprises traces and vias to interconnect pads for I/O, ground, and power signals throughout the microelectronics device;
- wherein the plurality of chips and the plurality of interconnect layers have electrical and mechanical bonds therebetween formed with nanoparticle ink or paste;
- wherein the plurality of chips and the plurality of interconnect layers are arranged to enhance density of the microelectronics package through edge connections such that at least one of the plurality of interconnect layers has a surface extending across surfaces of multiple chips within the plurality of chips and/or multiple interconnect layers within the plurality of interconnect layers.
A method of manufacturing a microelectronics device, comprising:
- arranging a plurality of chips and a plurality of interconnect layers, each of the at least one interconnect layers comprised of one of glass and ceramic with circuitry patterned thereon to provide power, ground and signal connections throughout the microelectronics device while using nanoparticle ink or paste to electrically and mechanically bond neighboring ones of the plurality of chips and the plurality of interconnect layers.
Dependencies are inferred from the claim text.