Semiconductor package having vertically stacked transistors and method of making the same
AssigneeAlpha and Omega Semiconductor International LP
InventorsYan Xun Xue, Sik Lui, Madhur Bobde, Long-Ching Wang, Zhiqiang Niu, Chunya Wen, Kuan-Hung Li, Lin Lv
Life of this patent
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Abstract
A semiconductor package comprising a lead frame, a vertically stacked field-effect transistor (FET) set, a source clip, a gate clip, and a molding encapsulation. The vertically stacked FET set comprises a first FET, and a second FET. The first FET is flipped. A method comprising the steps of providing a lead frame; attaching a vertically stacked FET set, attaching clip(s), forming a molding encapsulation; and applying a singulation process.
Claims20
A semiconductor package comprising:
- a lead frame comprising
- a die paddle;
- and
- a side paddle;
- a vertically stacked FET comprising
- a first field-effect transistor (FET) and a second FET in a back to back connection, the first FET comprising a source electrode and a gate electrode on a front surface of the first FET, the first FET being flipped and attached to the die paddle;
- the second FET comprising a source electrode and a gate electrode on a front surface of the second FET opposite the front surface of the first FET;
- a source clip connecting the source electrode of the second FET to the side paddle of the lead frame;
- and
- a molding encapsulation enclosing the first FET, the second FET, the source clip, and a majority portion of the lead frame.
A method for fabricating a semiconductor package, the method comprising the steps of:
- providing a lead frame comprising
- a die paddle;
- and
- a side paddle;
- attaching a vertically stacked field-effect transistor (FET) set comprising:
- a first field-effect transistor (FET) being flipped and attached to the die paddle, the first FET comprising a source electrode and a gate electrode on a front surface of the first FET;
- a second FET back to back attached to the first FET, the second FET comprising a source electrode and a gate electrode on a front surface of the second FET;
- attaching a source clip connecting the source electrode of the second FET to the side paddle of the lead frame;
- forming a molding encapsulation enclosing the first FET, the second FET, the source clip, and a majority portion of the lead frame;
- and
- applying a singulation process separating the semiconductor package from adjacent semiconductor packages.
A semiconductor package comprising:
- a vertically stacked FET comprising:
- a first field-effect transistor (FET) and a second FET in a back to back connection,
- the first FET comprising a source electrode and a gate electrode on a front surface of the first FET, and
- the second FET comprising a source electrode and a gate electrode on a front surface of the second FET opposite the front surface of the first FET;
- a molding encapsulation enclosing the first FET and the second FET, the molding encapsulation comprising:
- a bottom surface overlaying the front surface of the first FET;
- and
- a front surface overlaying the front surface of the second FET;
- a first gate metal section disposed on the bottom surface of the molding encapsulation, the first gate metal section being connected to the gate electrode of the first FET through a first gate connection via;
- a first source metal section disposed on the bottom surface of the molding encapsulation, the first source metal section being connected to the source electrode of the first FET through a first plurality of source connection vias;
- a second gate metal section disposed on the front surface of the molding encapsulation, the second gate metal section being connected to the gate electrode of the second FET through a second gate connection via;
- and
- a second source metal section disposed on the front surface of the molding encapsulation, the second source metal section being connected to the source electrode of the second FET through a second plurality of source connection vias.
Dependencies are inferred from the claim text.