Monolithic integration of hemt devices of normally-off type with hemt devices of normally-on type
AssigneeSTMicroelectronics International N.V.
InventorsPaolo COLPANI, Luisito LIVELLARA
Life of this patent
Estimating the term…
Loading patent…
AssigneeSTMicroelectronics International N.V.
InventorsPaolo COLPANI, Luisito LIVELLARA
Estimating the term…
A method for manufacturing a semiconductor die including an E-mode HEMT device at a first region of the semiconductor die and a D-mode MIS-HEMT device at a second region of the semiconductor die is provided. An example method includes: forming, on a heterostructure, a doped gate region of the E-mode HEMT device; forming a dielectric layer on the heterostructure and on the doped gate region; forming an insulating layer on the dielectric layer; forming a first gate opening exclusively at the second region, etching the first insulating layer but not the dielectric layer; forming a second gate opening, etching the first insulating layer and the dielectric layer exclusively at the doped gate region; and filling the first and the second gate openings with conductive material to form respective gate terminals of the D-mode MIS-HEMT and E-mode HEMT devices.
A method for manufacturing a semiconductor die including an E-mode HEMT or E-mode MIS-HEMT device at a first region of the semiconductor die and a D-mode MIS-HEMT device at a second region of the semiconductor die, the first region and the second region being at a distance from each other, wherein the method comprises:
A semiconductor die including an E-mode HEMT or E-mode MIS-HEMT device at a first region of the semiconductor die and a D-mode MIS-HEMT device at a second region of the semiconductor die, the first region and second region being at a distance from each other, the semiconductor die comprising:
Dependencies are inferred from the claim text.