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US 2026/0149532 A1Published application
Neural network to perform error detection and correction
AssigneeNVIDIA Corporation
InventorsYuan Gao, Yan Huang, Shaoran Li, James Hansen Delfeld, Christian Ibars Casas, Vikrama Ditya
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Abstract
Apparatuses, systems, and techniques to use one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals. In at least one embodiment, one or more EDC algorithms are to be performed on said one or more RAN signals based, at least in part, on one or more quality indicators of said one or more RAN signals.
Claims20
A processor comprising:
- one or more circuits to use one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals based, at least in part, on one or more quality indicators of the one or more RAN signals.
A system comprising:
- one or more processors to use one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals based, at least in part, on one or more quality indicators of the one or more RAN signals.
A method comprising:
- using one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals based, at least in part, on one or more quality indicators of the one or more RAN signals.
Dependencies are inferred from the claim text.