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US 2026/0149453 A1Published application
Divider circuit
AssigneeNXP B.V.
InventorsSanjay Kumar Wadhwa, Alok Kumar
Life of this patent
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Abstract
A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.
Claims20
A divider circuit comprising:
- a first differential latch circuit configured to
- receive a plurality of input signals, a plurality of clock signals, and inverted versions of the plurality of clock signals, and
- generate a plurality of latch signals based on the plurality of input signals, the plurality of clock signals, and the inverted versions of the plurality of clock signals;
- and
- a second differential latch circuit coupled to the first differential latch circuit, wherein the second differential latch circuit is configured to
- receive the plurality of latch signals, the plurality of clock signals, and the inverted versions of the plurality of clock signals, and
- generate a plurality of divided signals based on the plurality of latch signals, the plurality of clock signals, and the inverted versions of the plurality of clock signals, wherein the plurality of divided signals correspond to frequency divided versions of the plurality of clock signals and the plurality of input signals.
4 more elements
A divider circuit comprising:
- a plurality of differential latch circuits, wherein a first differential latch circuit of the plurality of differential latch circuits comprises first, second, third, and fourth inverters, a second differential latch circuit of the plurality of differential latch circuits comprises fifth, sixth, seventh, and eighth inverters, and wherein each inverter of the first through eighth inverters comprises a stack of first conductivity type transistors and a stack of second conductivity type transistors coupled to the stack of first conductivity type transistors, and wherein
- (i) the first through fourth inverters of the first differential latch circuit of the plurality of differential latch circuits are configured to
- receive a plurality of input signals, a plurality of clock signals, and inverted versions of the plurality of clock signals, and
- output a plurality of latch signals based on the plurality of input signals, the plurality of clock signals, and the inverted versions of the plurality of clock signals;
- and
- (ii) the fifth through eighth inverters of the second differential latch circuit of the plurality of differential latch circuits are configured to
- receive the plurality of latch signals, the plurality of clock signals, and the inverted versions of the plurality of clock signals, and
- output a plurality of divided signals based on the plurality of latch signals, the plurality of clock signals, and the inverted versions of the plurality of clock signals, wherein each divided signal of the plurality of divided signals corresponds to frequency divided versions of the plurality of clock signals and the plurality of input signals.
5 more elements
Dependencies are inferred from the claim text.