Performance islands for cpu clusters
AssigneeApple Inc.
InventorsBryan R. HINCH, John G. DORSEY, Ronit BANERJEE, Kushal DALMIA, Daniel A. CHIMENE, Jaidev P. PATWARDHAN
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AssigneeApple Inc.
InventorsBryan R. HINCH, John G. DORSEY, Ronit BANERJEE, Kushal DALMIA, Daniel A. CHIMENE, Jaidev P. PATWARDHAN
Estimating the term…
Embodiments include an asymmetric multiprocessing (AMP) system having two or more central processing unit (CPU) clusters of a first core type and a CPU cluster of a second core type. Some embodiments include determining a control effort for an active thread group, and assigning the thread group to a first performance island according to the control effort range of the first performance island. The first performance island can include a first CPU cluster of the first core type, where a second performance island includes a second CPU cluster of the first core type, where the second performance island corresponds to a different control effort range than the first performance island. Some embodiments include assigning the first CPU cluster as a preferred CPU cluster of the first thread group, and transmitting a first signal identifying the first CPU cluster as the preferred CPU cluster assigned to the first thread group.
(canceled)
A system on a chip (SoC), comprising:
An apparatus, comprising a central processing unit (CPU) including a first CPU cluster and a second CPU cluster, wherein the CPU is configured to:
Dependencies are inferred from the claim text.