System-on-chip including a plurality of chips and method of operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYoungduke SEO, Sungcheol PARK, Joonyoung CHANG, Geunho CHOI
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Abstract
A system-on-chip (SoC) includes a plurality of chips connected to each other. Among the plurality of chips, a first chip may include a plurality of first interfaces, respectively disposed on edges of the first chip, a first central processing unit (CPU) configured to execute a first program, and a first interconnect configured to transmit a first address code to a (1-1)-th interface corresponding to a first number of first interface bits of the first address code stored to correspond to the first program in response to a first request corresponding to the first program being received from the first CPU.
Claims20
A system-on-chip (SoC) comprising:
- a plurality of chips connected to each other,
- whereina first chip among the plurality of chips comprises,
- a plurality of first interfaces respectively arranged on edges of the first chip,
- a first central processing unit (CPU) configured to execute a first program, and
- a first interconnect configured to transmit a first address code to a (1-1)-th interface, the (1-1)-th interface corresponding to a first number of first interface bits of the first address code stored to correspond to the first program, the first interconnect configured to transmit the first address code in response to a first request being received from the first CPU, the first request corresponding to the first program.
A method of operating a system-on-chip (SoC) comprising a plurality of chips, the method comprising:
- running a first program by a first central processing unit (CPU) included in a first chip among the plurality of chips;
- transmitting a first address code to a (1-1)-th interface corresponding to a first number of first interface bits of the first address code stored to correspond to the first program, in response to a first request corresponding to the first program being received from the first CPU;
- generating, by the (1-1)-th interface, a second address code by replacing the first interface bits with a second number of second interface bits, the generating the second address code starting from a least significant bit of a first user code stored to correspond to the first program;
- and
- transmitting the second address code to a (2-1)-th interface of a second chip adjacent to the (1-1)-th interface, the second chip among the plurality of chips.
A system-on-chip (SoC) comprising:
- a first chip and a second chip adjacent to each other,
- wherein the first chip comprises,
- a (1-1)-th interface on an edge adjacent to the second chip,
- a first central processing unit (CPU) configured to execute a first program, and
- a first interconnect configured to transmit a first address code to a (1-1)-th interface corresponding to a first number of first interface bits of the first address code stored to correspond to the first program, the transmitting the first address code in response to a first request corresponding to the first program being received from the first CPU,
- and the (1-1)-th interface is configured to,
- generate a second address code by replacing the first interface bits with a second number of second interface bits of a first user code stored to correspond to the first program, and
- transmit the second address code to the second chip through a (2-1)-th interface adjacent to the (1-1)-th interface.
Dependencies are inferred from the claim text.