Low cost and low latency logical unit erase

A memory device, comprising:

• a controller, wherein the controller comprises:
• at least one hardware processor;
• and
• memory storing instructions that, when executed by the at least one hardware processor, cause the at least one hardware processor to perform operations comprising:
• receiving data to write to a physical address (PA) of a memory array;
• generating a logical to physical (L2P) table to map a logical block address (LBA) of the data to the PA of the memory array;
• encrypting the LBA in the L2P table using an encryption key;
• changing the encryption key in response to receiving an erase command for the data;
• and
• decrypting the encrypted LBA in the L2P table using the changed encryption key in response to receiving a read command of the data after receiving the erase command.

A non-transitory machine-readable medium, storing instructions that, when executed by a memory device, cause the memory device to perform operations comprising:

• receiving data to write to a physical address (PA) of a memory array;
• generating a logical to physical (L2P) table to map a logical block address (LBA) of the data to the PA of the memory array;
• encrypting the LBA in the L2P table using an encryption key;
• changing the encryption key in response to receiving an erase command for the data;
• and
• decrypting the encrypted LBA in the L2P table using the changed encryption key in response to receiving a read command of the data after receiving the erase command.