Techniques to implement a data-aware cache replacement policy
AssigneeIntel Corporation
InventorsKeqiang WU, Adrian C. MOGA, Yuan ZHOU, Krishnaswamy VISWANATHAN, Christopher J. HUGHES
Life of this patent
Estimating the term…
Abstract
Examples include techniques to implement a data-aware cache replacement policy. The techniques include indicating, to a cache controller, that data to be included in a cache line is likely to be reused. The indication of likely-to-be-reused data is to be used by the cache controller to determine when the data is to be evicted or replaced in the cache.
Claims21
-23. (canceled)
An apparatus comprising:
- a plurality of processing cores;
- a cache;
- and
- a cache controller configured to:
- receive an indication of whether data to be included in a cache line of the cache is likely to be reused;
- set a priority bit for the data to be included in the cache line based on an indication that the data is likely to be reused;
- and
- set an age bit for the data to indicate an order of access for the cache line to store the data to the cache compared to at least one other cache line to be configured to separately store data to the cache, wherein the priority bit and the age bit are to be used to determine when to evict the data included in the cache line from the cache.
At least one machine readable medium comprising a plurality of instructions that in response to being executed by a cache controller of a processor cache, causes the cache controller to:
- receive an indication of whether data to be included in a cache line of the processor cache is likely to be reused;
- set a priority bit for the data to be included in the cache line based on an indication that the data is likely to be reused;
- and
- set an age bit for the data to indicate an order of access for the cache line to store the data to the processor cache compared to at least one other cache line to be configured to separately store data to the processor cache, wherein the priority bit and the age bit are to be used to determine when to evict the data included in the cache line from the processor cache.
A method comprising:
- receiving, at a cache controller of a processor cache, an indication of whether data to be included in a cache line of the processor cache is likely to be reused;
- setting a priority bit for the data to be included in the cache line based on an indication that the data is likely to be reused;
- and
- setting an age bit for the data to indicate an order of access for the cache line to store the data to the processor cache compared to at least one other cache line to be configured to separately store data to the processor cache, wherein the priority bit and the age bit are to be used to determine when to evict the data included in the cache line from the processor cache.
Dependencies are inferred from the claim text.