Redundancy and swapping scheme for memory repair
AssigneeMicron Technology, Inc.
InventorsJaeil Kim, Simon J. Lovett
Life of this patent
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Abstract
A memory device can include a bank of memory cells. The bank of memory cells can include multiple groups of columns of memory cells. The memory device can include controller circuitry to provide information pertaining to a column repair redundancy swap for repairing a selected group of the plurality of groups at row address strobe (RAS) time. Upon detection of an error condition in at least one group of columns of memory cells, the controller circuitry can implement the column repair redundancy swap on the corresponding group.
Claims20
An apparatus, comprising:
- a bank of memory cells;
- and
- a controller coupled to the bank of memory cells, the controller configured to:
- generate, during a row address strobe (RAS) time, information corresponding to a column redundancy swap operation, the information including at least one of a column redundancy signal and a swap enable signal for a group of memory cells in the bank of memory cells;
- and
- responsive to detecting that an error condition has occurred in a failed group of memory cells, implement the column redundancy swap operation for at least one column of the failed group of memory cells.
A method, comprising:
- generating, during a row address strobe (RAS) time, information corresponding to a column redundancy swap operation, the information including at least one of a column redundancy signal and a swap enable signal for a group of memory cells in a bank of memory cells;
- and
- performing the column redundancy swap operation for at least one column of failed group of memory cells responsive to detecting that an error condition has occurred in the failed group of memory cells.
A non-transitory machine-readable medium storing instructions which, when executed by a processor, cause the processor to:
- generate, during a row address strobe (RAS) time, information corresponding to a column redundancy swap operation, the information including at least one of a column redundancy signal and a swap enable signal for a group of memory cells in a bank of memory cells;
- and
- cause the column redundancy swap operation to be performed for at least one column of a failed group of memory cells responsive to detecting that an error condition has occurred in the failed group of memory cells.
Dependencies are inferred from the claim text.