Reception signal quality monitor
AssigneeThine Electronics, Inc.
InventorsTomohiro ISHIDA, Shunichi KUBO
Life of this patent
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Abstract
The phase adjustment circuit 11 of this receiving signal quality monitor can sweep the phase of the sampling clock signal φe of the reference sampler within a phase range of several times the unit interval (UI) of the serial data signal. The first synchronization circuit 13A receives the first output signal of one sampler in the plurality of data reception samplers and the second output signal of the reference sampler SMe. The comparison logic circuit 15 receives the first and second output signals synchronously output from the first synchronization circuit 13A and outputs a comparison result related to the quality of the received signal.
Claims9
A receiving signal quality monitor, comprising:
- a plurality of data reception samplers connected in parallel, each receiving a serial data signal and being input with a sampling clock signal, resulting in multi-phase sampling clock signals being input to the data reception samplers;
- a reference sampler configured to receive the serial data signal;
- a phase adjustment circuit configured to allow a phase of a sampling clock signal input to the reference sampler to be swept within a phase range corresponding to N times a unit interval (UI) of the serial data signal, where 2≤N;
- a first synchronization circuit to which an output signal of one of the plurality of data reception samplers and an output signal of the reference sampler are input;
- and
- a comparison logic circuit to which two output signals synchronously output from the first synchronization circuit are input.
Dependencies are inferred from the claim text.