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US 2026/0144153 A1Published application
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorSeokgeun Ahn
Life of this patent
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Abstract
A semiconductor package includes a logic chip having a first front surface and a first rear surface opposite to the first front surface, including first connection pads and through-electrodes electrically connected to at least one of the first connection pads; a plurality of memory chips each having a second front surface and a second rear surface and including second connection pads on the second front surface, and being offset-stacked on the first rear surface of the logic chip such that the second connection pads face upwardly; wires connecting the through-electrodes and the second connection pads; an encapsulation layer on the logic chip and encapsulating the plurality of memory chips and the conductive wires; and bumps on the first front surface and electrically connected to the first connection pads.
Claims20
A semiconductor package comprising:
- a logic chip having a first front surface and a first rear surface opposite to the first front surface, the logic chip including first connection pads on the first front surface and through-electrodes extending to the first front surface and the first rear surface and electrically connected to at least one of the first connection pads;
- a plurality of memory chips each having a second front surface and a second rear surface opposite to the second front surface, each including second connection pads on the second front surface, and the plurality of memory chips being offset-stacked on the first rear surface of the logic chip such that the second connection pads face upward;
- wires connecting the through-electrodes of the logic chip and the second connection pads of the plurality of memory chips;
- an encapsulation layer on the logic chip and encapsulating the plurality of memory chips and the conductive wires;
- and
- bumps on the first front surface and electrically connected to the first connection pads.
3 more elements
A semiconductor package comprising:
- a logic chip having a first front surface and a first rear surface opposite to the first front surface, the logic chip including first connection pads on the first front surface and through-electrodes extending to the first front surface and the first rear surface and electrically connected to at least one of the first connection pads;
- a plurality of memory chips each having a second front surface and a second rear surface opposite to the second front surface, each including second connection pads on the second front surface, and the plurality of memory chips being offset-stacked on the first rear surface of the logic chip such that the second connection pads face upward;
- wires connecting the through-electrodes of the logic chip and the second connection pads of the plurality of memory chips;
- an encapsulation layer on the logic chip and encapsulating the plurality of memory chips and the conductive wires;
- and
- bumps on the first front surface and electrically connected to the first connection pads, wherein the logic chip has a first region in which the through-electrodes are arranged, a second region adjacent to one side of the first region, and a third region adjacent to an opposite side of the first region,
- wherein the plurality of memory chips include first stacked chips disposed on the second region, and second stacked chips disposed on the third region, wherein the first stacked chips are disposed such that the second connection pads thereof are adjacent to the one side of the first region, and
- wherein the second stacked chips are disposed such that the second connection pads thereof are adjacent to the opposite side of the first region.
5 more elements
A semiconductor package comprising:
- a first semiconductor chip having a first front surface and a first rear surface opposite to the first front surface, the first semiconductor chip including first connection pads on the first front surface and through-electrodes extending to the first front surface and the first rear surface and electrically connected to at least one of the first connection pads;
- a plurality of second semiconductor chips each having a second front surface and a second rear surface opposite to the second front surface, each including second connection pads on the second front surface, and the plurality of second semiconductor chips being offset-stacked on the first rear surface of the first semiconductor chip such that the second connection pads face upward;
- wires connecting the through-electrodes of the first semiconductor chip and the second connection pads of the plurality of second semiconductor chips;
- an encapsulation layer on the first semiconductor chip and encapsulating the plurality of second semiconductor chips and the conductive wires;
- and
- bumps on the first front surface and electrically connected to the first connection pads,
- wherein the encapsulation layer has a first side surface surrounding the plurality of second semiconductor chips,
- wherein the first semiconductor chip has a second side surface surrounding the through-electrodes, and
- wherein the first side surface and the second side surface are coplanar with each other.
6 more elements
Dependencies are inferred from the claim text.