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US 2026/0144148 A1Published application
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorInjae LEE
Life of this patent
Estimating the term…
Abstract
A semiconductor package may include a package substrate, a multilayer ceramic capacitor on the package substrate, a semiconductor device on the package substrate and spaced apart from the multilayer ceramic capacitor in a horizontal direction, and an external wiring on the package substrate and providing an electrical connection path between the multilayer ceramic capacitor and the semiconductor device.
Claims20
A semiconductor package, comprising:
- a package substrate;
- a multilayer ceramic capacitor on the package substrate;
- a semiconductor device on the package substrate, the semiconductor device spaced apart from the multilayer ceramic capacitor in a horizontal direction;
- and
- an external wiring on the package substrate, the external wiring providing an electrical connection path between the multilayer ceramic capacitor and the semiconductor device.
2 more elements
A semiconductor package, comprising:
- a package substrate comprising a base layer, a plurality of upper connection pads on an upper surface of the base layer, a plurality of lower connection pads on a lower surface of the base layer, and board wiring electrically connecting some of the plurality of upper connection pads to some of the plurality of lower connection pads;
- a multilayer ceramic capacitor on the package substrate;
- a semiconductor device on the package substrate, the semiconductor device spaced apart from the multilayer ceramic capacitor in a horizontal direction;
- and
- an external wiring on the package substrate, the external wiring providing an electrical connection path between the multilayer ceramic capacitor and the semiconductor device.
2 more elements
A semiconductor package, comprising:
- a package substrate comprising a base layer, a plurality of upper connection pads on an upper surface of the base layer, a plurality of lower connection pads on a lower surface of the base layer, and board wiring electrically connecting some of the plurality of upper connection pads to some of the plurality of lower connection pads;
- a multilayer ceramic capacitor on the package substrate, the multilayer ceramic capacitor comprising a ceramic body, a first external electrode, a second external electrode, the ceramic body comprising a plurality of first internal electrodes and a plurality of second internal electrodes alternating with each other, with a dielectric layer interposed therebetween, the first external electrode and the second external electrode being at both side edges of the ceramic body, respectively, the first external electrode connected to the plurality of first internal electrodes, the second external electrode connected to the plurality of second internal electrodes;
- a semiconductor device on the package substrate, the semiconductor device spaced apart from the multilayer ceramic capacitor in a horizontal direction;
- and
- an external wiring on the package substrate, the external wiring providing an electrical connection path between the multilayer ceramic capacitor and the semiconductor device,
- wherein the plurality of upper connection pads comprise one or more first upper connection pads and one or more second upper connection pads, the one or more first upper connection pads connected to the multilayer ceramic capacitor through a first connection member, the one or more second upper connection pads connected to the semiconductor device through a second connection member.
3 more elements
Dependencies are inferred from the claim text.