Semiconductor package including interposer having glass core layer

A semiconductor package, comprising:

• a package substrate;
• an interposer structure on the package substrate;
• and
• semiconductor chips on the interposer structure, and the semiconductor chips electrically connected to the package substrate through the interposer structure,
• wherein the interposer structure comprises:
• a glass core layer;
• first through-electrodes penetrating the glass core layer;
• bridge structures on the first through-electrodes;
• bridge connection bumps between the bridge structures and the first through-electrodes;
• and
• bridge mold layers between the bridge structures and the glass core layer, and covering side surfaces of the bridge connection bumps,
• wherein each of the bridge structures comprises a base substrate and bridge through-electrodes penetrating through the base substrate and each bridge through-electrode vertically overlapping a respective bridge connection bump.

A semiconductor package, comprising:

• a package substrate;
• an interposer structure on the package substrate;
• and
• semiconductor chips on the interposer structure and electrically connected to the package substrate through the interposer structure,
• wherein the interposer structure comprises:
• a glass core layer;
• first through-electrodes penetrating through the glass core layer;
• second through-electrodes penetrating through the glass core layer and spaced apart from the first through-electrodes;
• semiconductor interconnection dies with each semiconductor interconnection die disposed on corresponding first through-electrodes;
• redistribution structures with each redistribution structure on corresponding second through-electrodes;
• bridge connection bumps with each bridge bump between a corresponding semiconductor interconnection die and a corresponding first through-electrode;
• and
• bridge mold layers with each bridge mold layer between a corresponding semiconductor interconnection die and the glass core layer and covering side surfaces of corresponding bridge connection bumps,
• each of the semiconductor interconnection dies comprises:
• a base substrate;
• bridge through-electrodes penetrating through the base substrate and each bridge through-electrode vertically overlapping a respective bridge connection bump;
• bridge upper pads with each bridge upper pad on a respective bridge through-electrodes;
• and
• bridge lower pads with each bridge lower pad below a respective bridge through-electrodes, and
• each of the bridge connection bumps are on a lower surface of a respective lower pad and an upper surface of a respective first through-electrode.