Semiconductor device and fabrication method thereof
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsQuan Zhang, Lan Yao, Lu Zhou
Life of this patent
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Abstract
A method of fabricating a semiconductor device includes forming a first shallow trench isolation structure in a first region of a substrate and second shallow trench isolation structures in a second region of the substrate. The method also includes forming a mask layer over the substrate, the first shallow trench isolation structure, and the second shallow trench isolation structures. The method further includes etching the mask layer and second shallow trench isolation structures in the second region sequentially to form a semiconductor protrusion between the second shallow trench isolation structures.
Claims20
A memory device, comprising:
- an array of memory cells;
- and
- a peripheral circuit coupled to the array of memory cells and comprising a substrate, a first transistor, and a second transistor,
- wherein the first transistor comprises a first gate dielectric layer and a first gate layer, and the second transistor comprises a second gate dielectric layer and a second gate layer;
- wherein the substrate comprises a first semiconductor protrusion and a second semiconductor protrusion;
- wherein the first gate layer surrounds the first semiconductor protrusion on three sides and the second gate layer surrounds the second semiconductor protrusion on three sides;
- and
- wherein a thickness of the first gate dielectric layer in a first direction is different from a thickness of the second gate dielectric layer in a first direction.
A memory device, comprising:
- an array of memory cells;
- and
- a peripheral circuit coupled to the array of memory cells and comprising a planar transistor and a first fin field-effect transistor,
- wherein the planar transistor comprises a first gate dielectric layer and a first gate layer, and the first fin field-effect transistor comprises a second gate dielectric layer and a second gate layer;
- and
- wherein a thickness of the first gate dielectric layer in a first direction is larger than a thickness of the second gate dielectric layer in the first direction.
A memory system, comprising:
- a memory device;
- and
- a memory controller coupled to the memory device and configured to control the memory device,
- wherein the memory device comprises:
- an array of memory cells;
- and
- a peripheral circuit coupled to the array of memory cells and comprising a substrate, a first transistor, and a second transistor,
- wherein the first transistor comprises a first gate dielectric layer and a first gate layer, and the second transistor comprises a second gate dielectric layer and a second gate layer;
- wherein the substrate comprises a first semiconductor protrusion and a second semiconductor protrusion;
- wherein the first gate layer surrounds the first semiconductor protrusion on three sides and the second gate layer surrounds the second semiconductor protrusion on three sides;
- and
- wherein a thickness of the first gate dielectric layer in a first direction is different from a thickness of the second gate dielectric layer in a first direction.
Dependencies are inferred from the claim text.