US 2026/0143826 A1 · SOLAR CELL EMITTER REGION FABRICATION WITH DIFFERENTIATED P-TYPE AND N-TYPE LAYOUTS AND INCORPORATING DOTTED DIFFUSION

Abstract

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type layouts and incorporating dotted diffusion, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is on a first thin dielectric layer on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is on a second thin dielectric layer on the back surface of the substrate. The second polycrystalline silicon emitter region has a vertical thickness less than a vertical thickness of the first polycrystalline silicon emitter region.

Claims20

Dependent claims

A method of fabricating a solar cell, the method comprising:

forming an N+ polycrystalline silicon layer on a thin dielectric layer on a back surface of a substrate;
forming a boron doped silica glass (BSG) layer on the N+ polycrystalline silicon layer;
forming an amorphous silicon (aSi) layer on the BSG layer;
performing laser ablating to form an opening in the aSi layer and to dope a region of the N+ polycrystalline silicon layer and to leave outer unmodified regions of the N+ polycrystalline silicon layer exposed;
etching to remove the exposed outer unmodified regions of the N+ polycrystalline silicon layer to form N+ polycrystalline silicon emitter regions and a remnant polycrystalline silicon region beneath a boron-doped silicon cap;
etching to remove the boron-doped silicon cap and to leave remaining a remnant polycrystalline silicon region;
and
doping the remnant polycrystalline silicon region to form a P+ polycrystalline silicon emitter region.

5 more elements

A method of fabricating a solar cell, the method comprising:

providing a substrate having a light-receiving surface and a back surface;
forming a first polycrystalline silicon emitter region of a first conductivity type on a first thin dielectric layer on the back surface of the substrate;
forming a second polycrystalline silicon emitter region of a second, different, conductivity type on a second thin dielectric layer on the back surface of the substrate, wherein the second polycrystalline silicon emitter region has a vertical thickness less than a vertical thickness of the first polycrystalline silicon emitter region, wherein the second polycrystalline emitter region has a bottommost surface at a same level as a bottommost surface of the first polycrystalline silicon emitter region, and wherein the second polycrystalline silicon emitter region does not vertically overlap with the first polycrystalline silicon emitter region;
forming an insulating layer on a top surface of the first polycrystalline silicon emitter region, on a top surface of the second polycrystalline silicon emitter region, along sides of second polycrystalline silicon emitter region, and along a side of the first polycrystalline silicon emitter region, wherein the insulating layer has a vertical thickness over the first polycrystalline silicon emitter region greater than a vertical thickness of the insulating layer over the second polycrystalline silicon emitter region;
and
forming a conductive contact structure over and extending through the insulating layer to directly contact the second polycrystalline silicon emitter region, wherein the conductive contact structure is vertically overlapping with but separated from the first polycrystalline silicon emitter region along a vertical axis.

3 more elements

Dependencies are inferred from the claim text.

Solar cell emitter region fabrication with differentiated p-type and n-type layouts and incorporating dotted diffusion

Life of this patent

Solar cell emitter region fabrication with differentiated p-type and n-type layouts and incorporating dotted diffusion

Life of this patent

Abstract

Claims20