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US 2026/0143776 A1Published application
Semiconductor device and methods of formation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTung-Yang LIN, Ruey-Hsin LIU
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Abstract
A deep trench structure may be formed to include a doped polysilicon core and dielectric isolation layers on the sidewalls of the doped polysilicon core. The deep trench structure may be provided as a deep trench isolation structure that laterally surrounds transistors in a semiconductor device. Additionally and/or alternatively, the deep trench structure may be included in a high-voltage transistor as a vertical drain region that extends into a semiconductor layer of a semiconductor device.
Claims20
A semiconductor device, comprising:
- a source/drain region in a doped semiconductor region;
- an elongated structure having a doped insert,
- wherein the elongated structure is located in the doped semiconductor region, and
- wherein a height of the elongated structure is greater than a width of the elongated structure;
- a first dielectric layer along sidewalls of the doped insert of the elongated structure,
- wherein the first dielectric layer extends along the height of the elongated structure, and
- wherein the width of the elongated structure is across the doped insert and the first dielectric layer;
- a gate structure over the doped semiconductor region and laterally between the source/drain region and the elongated structure;
- a second dielectric layer between the doped semiconductor region and the gate structure,
- wherein the second dielectric layer is laterally between the source/drain region and the elongated structure;
- a first contact structure above and coupled to the source/drain region;
- and
- a second contact structure above and coupled to the doped insert of the elongated structure,
- wherein the first contact structure and the second contact structure are located adjacent to opposing sides of the gate structure.
11 more elements
A method, comprising:
- etching a doped semiconductor layer of a semiconductor device to form a recess in the doped semiconductor layer;
- depositing a conformal dielectric layer on sidewalls and on a bottom surface of the recess;
- etching the conformal dielectric layer to remove a portion of the conformal dielectric layer from the bottom surface of the recess to form dielectric isolation layer segments on the sidewalls of the recess,
- wherein a first dielectric isolation layer segment of the dielectric isolation layer segments is located on a first sidewall of the sidewalls, and a second dielectric isolation layer segment dielectric isolation layer segments is located on a second opposing sidewall of the sidewalls;
- depositing material in an area in the recess between the dielectric isolation layer segments to form a doped insert,
- wherein the dielectric isolation layer segments and the doped insert correspond to an elongated structure of the semiconductor device;
- forming a source/drain region of a transistor structure in the doped semiconductor layer,
- wherein the source/drain region and the elongated structure are spaced apart by a portion of the doped semiconductor layer;
- and
- forming a gate structure of the transistor structure on the doped semiconductor layer,
- wherein the gate structure is located laterally between the source/drain region and the elongated structure.
8 more elements
A semiconductor device, comprising:
- a first doped semiconductor region above a bottom semiconductor layer of the semiconductor device;
- a second doped semiconductor region in the first doped semiconductor region,
- wherein the first doped semiconductor region comprises a first dopant type, and
- wherein the second doped semiconductor region comprises a second dopant type that is different from the first dopant type;
- a first type transistor structure in the first doped semiconductor region;
- a second type transistor structure in the second doped semiconductor region;
- and
- a deep trench isolation (DTI) structure laterally surrounding the first type transistor structure and the second type transistor structure,
- wherein the DTI structure comprises a doped polysilicon insert.
6 more elements
Dependencies are inferred from the claim text.