Multi-Gate Device And Method Of Fabrication Thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsI-Sheng CHEN, Yee-Chia YEO, Chih Chieh YEH, Cheng-Hsien WU
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Abstract
A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.
Claims20
A semiconductor device, comprising:
- a plurality of semiconductor channel layers disposed over a substrate;
- a first portion of a gate structure surrounding at least one semiconductor channel layer of the plurality of semiconductor channel layers;
- a second portion of the gate structure disposed over a topmost semiconductor channel layer of the plurality of channel layers;
- and
- a first metal layer that at least partially wraps around the first portion of the gate structure surrounding the at least one semiconductor channel layer;
- wherein a space between adjacent semiconductor channel layers of the plurality semiconductor channel layers is free of the first metal layer.
A semiconductor device, comprising:
- first and second channel layers vertically stacked over a substrate;
- an interposing feature including at least an interfacial layer wrapping around the first and second channel layers;
- and
- a metal layer disposed along sidewalls of the interposing feature;
- wherein a space between the first and second channel layers is free of the metal layer;
- and
- wherein a distance between the metal layer and the interfacial layer is less than or equal to a predetermined threshold.
A semiconductor device, comprising:
- a plurality of channel layers stacked over a substrate;
- a dielectric layer surrounding at least one channel layer of the plurality of channel layers;
- a capping layer at least partially wrapping around the dielectric layer;
- and
- a metal layer disposed over the capping layer and partially wrapping around the dielectric layer;
- wherein a space between adjacent channel layers of the plurality channel layers is free of the metal layer.
Dependencies are inferred from the claim text.