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US 2026/0143737 A1Published application
Semiconductor device and semiconductor device manufacturing method
AssigneeSamsung Electronics Co., Ltd.
InventorsEunji YANG, Baekwon PARK, Changhyun KIM
Life of this patent
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Abstract
A semiconductor device includes a substrate, a source electrode on the substrate, a drain electrode being apart from the source electrode, a channel connecting the source electrode to the drain electrode and including a two-dimensional material, a gate insulating layer on the channel, and a gate electrode on the gate insulating layer, wherein the gate electrode includes an overlap area facing the source electrode in a vertical direction.
Claims20
A semiconductor device comprising:
- a substrate;
- a source electrode on the substrate;
- a drain electrode on the substrate, the drain electrode being apart from the source electrode;
- a channel being between the source electrode and the drain electrode, the channel connecting the source electrode to the drain electrode, the channel comprising a two-dimensional material;
- a gate insulating layer on the channel;
- and
- a gate electrode on the gate insulating layer, wherein
- the gate electrode has an asymmetrical structure in terms of an overlap area facing a corresponding one of the source electrode and the drain electrode in a vertical direction, and
- the gate electrode comprises the overlap area facing the source electrode in the vertical direction.
6 more elements
A semiconductor device comprising:
- a substrate;
- a source electrode on the substrate;
- a drain electrode on the substrate, the drain electrode being apart from the source electrode;
- a channel being between the source electrode and the drain electrode, the channel connecting the source electrode to the drain electrode to the channel, the channel comprising a two-dimensional material, the channel comprising a plurality of channel layers, the plurality of channel layers being apart from each other in a direction away from the substrate;
- a spacer between a corresponding pair of the plurality of channel layers, the spacer supporting the corresponding pair of the plurality of channel layers;
- a gate insulating layer on the plurality of channel layers;
- and
- a gate electrode on the gate insulating layer, wherein
- the spacer comprises a first spacer adjacent to the source electrode and a second spacer adjacent to the drain electrode, and
- the first spacer has a smaller thickness than the second spacer.
7 more elements
A semiconductor device manufacturing method comprising:
- alternately stacking a sacrificial layer and a channel on a substrate, the channel comprising a two-dimensional material;
- patterning a stack structure of the sacrificial layer and the channel by using a mask;
- forming a source electrode and a drain electrode on both sides of the patterned stack structure, respectively;
- removing the sacrificial layer such that the channel is suspended between the source electrode and the drain electrode, the channel including a plurality of channel layers, the plurality of channel layers being apart from each other in a direction perpendicular to the substrate;
- forming a first spacer adjacent to the source electrode and a second spacer adjacent to the drain electrode, between an adjacent pair of the plurality of channel layers;
- depositing a gate insulating layer on the channel;
- and
- depositing a gate electrode on the gate insulating layer,
- wherein the first spacer has a smaller thickness than the second spacer.
6 more elements
Dependencies are inferred from the claim text.