Overland synchronization signal (ss) block structures and cell detection procedures
AssigneeLenovo (United States) Inc.
InventorsKarthikeyan GANESAN, Ali Ramadan ALl, Ravi KUCHIBHOTLA
Life of this patent
Estimating the term…
Abstract
Various aspects of the present disclosure relate to a signaling mechanism, such as a mechanism that implements an overlaid synchronization signal (SS) block structure or design, to detect minimized signals transmitted by the base station during initial synchronization procedures. For example, the new signaling may comprise SS blocks that include overlaid sequence carrying information, such as a synchronization signal overlaid within an ON duration of an on-off keying (OOK) pulse.
Claims20
A network entity for wireless communication, comprising:
- at least one memory;
- and
- at least one processor coupled with the at least one memory and configured to cause the network entity to:
- configure an overlaid synchronization signal (SS) block (SS block) to include an overlaid orthogonal frequency division multiplexing (OFDM) sequence within an ON-OFF keying (OOK) ON symbol,
- wherein the overlaid OFDM sequence comprises an SS having a primary synchronization signal (PSS) and a secondary synchronization signal (SSS) overlaid within one or more OOK ON symbols included in a binary sequence of the OOK;
- and
- transmit the configured overlaid SS block in an OFDM symbol included in a slot.
A method performed by a network entity, the method comprising:
- configuring an overlaid synchronization signal (SS) block (SS block) to include an overlaid orthogonal frequency division multiplexing (OFDM) sequence within an ON-OFF keying (OOK) ON symbol,
- wherein the overlaid OFDM sequence comprises an SS having a primary synchronization signal (PSS) and a secondary synchronization signal (SSS) overlaid within one or more OOK ON symbols included in a binary sequence of the OOK;
- and
- transmitting the configured overlaid SS block in an OFDM symbol included in a slot.
A user equipment (UE) for wireless communication, comprising:
- at least one memory;
- and
- at least one processor coupled with the at least one memory and configured to cause the UE to:
- receive an overlaid synchronization signal (SS) block (SS block) that includes an overlaid orthogonal frequency division multiplexing (OFDM) sequence within an ON-OFF keying (OOK) ON symbol,
- wherein the overlaid OFDM sequence comprises an SS having a primary synchronization signal (PSS) and a secondary synchronization signal (SSS) overlaid within OOK ON symbols of a binary sequence of the OOK;
- and
- detect the SS within the overlaid SS block.
A processor for wireless communication, the processor comprising:
- at least one controller coupled with at least one memory and configured to cause the processor to:
- receive an overlaid synchronization signal (SS) block (SS block) that includes an overlaid orthogonal frequency division multiplexing (OFDM) sequence within an ON-OFF keying (OOK) ON symbol,
- wherein the overlaid OFDM sequence comprises an SS having a primary synchronization signal (PSS) and a secondary synchronization signal (SSS) overlaid within OOK ON symbols of a binary sequence of the OOK;
- and
- detect the SS within the overlaid SS block.
Dependencies are inferred from the claim text.