US 2026/0142792 A1 · DETERMINISTIC JITTER DETECTION AND MITIGATION FOR FREQUENCY DIVIDER CIRCUITRY

Abstract

A communication system includes correction circuitry. The correction circuitry includes detection circuitry and clock correction circuitry. The detection circuitry determines a first correction value based on a first rising edge and a second rising edge of a divided clock signal. The clock correction circuitry receives a first clock signal, a second clock signal and the first correction value, and generates a first adjusted clock signal and a second adjusted clock signal based on the first correction value. The first clock signal and the second clock signal. The first adjusted clock signal and the second adjusted clock signal are used by divider circuitry to generate the divided clock signal. A frequency of the divided clock signal is less than a frequency of the first clock signal and the second clock signal.

Claims20

Dependent claims

A correction circuitry comprising:

detection circuitry configured to determine a first correction value based on a first rising edge and a second rising edge of a divided clock signal;
and
clock correction circuitry configured to receive a first clock signal, a second clock signal and the first correction value, and generate a first adjusted clock signal and a second adjusted clock signal based on the first correction value, the first clock signal and the second clock signal, wherein the first adjusted clock signal and the second adjusted clock signal are used by divider circuitry to generate the divided clock signal, and wherein a frequency of the divided clock signal is less than a frequency of the first clock signal and the second clock signal.

A communication system comprising:

transceiver circuitry connecting a first integrated circuit (IC) device with a second IC device, the transceiver circuitry comprising:
detection circuitry configured to determine a first correction value based on a first rising edge and a second rising edge of a divided clock signal;
clock correction circuitry configured to receive a first clock signal, a second clock signal and the first correction value, and generate a first adjusted clock signal and a second adjusted clock signal based on the first correction value, the first clock signal and the second clock signal;
and
clock divider circuitry configured to generate the divided clock signal from the first adjusted clock signal and the second adjusted clock signal, wherein a frequency of the divided clock signal is less than a frequency of the first clock signal and the second clock signal.

2 more elements

Dependencies are inferred from the claim text.

Deterministic jitter detection and mitigation for frequency divider circuitry

Life of this patent

Deterministic jitter detection and mitigation for frequency divider circuitry

Life of this patent

Abstract

Claims20