Fast multi-payload-length error-correcting system and methods
AssigneeMicron Technology, Inc.
InventorsMarco Sforzin, Christophe Vincent Antoine Laurent
Life of this patent
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Abstract
Systems and methods for fast multi-length payload error correcting includes at least a decoder circuit. The decoder circuit receives a first input and receives a second input. The decoder circuit generates, based on the first input, a first decoded payload. The first decoded payload includes at least a first data or a first length and a first flip bit. The decoder circuit generates, based on the second input, a second decoded payload. The second decoded payload includes at least a second data of a second length and a second flip bit, the second length being different from the first length.
Claims20
An apparatus, comprising:
- a decoder circuit, configured to:
- receive a first input;
- generate first syndrome coefficients based on the first input;
- receive a second input;
- generate second syndrome coefficients based on the second input;
- using the first input and the first syndrome coefficients, decode a first payload, the first payload comprising first data of a first length and a first flip bit;
- and
- using the second input and the second syndrome coefficients, decode a second payload, the second payload comprising second data of a second length and a second flip bit;
- wherein the first length of the first data is less than the second length of the second data.
An apparatus, comprising:
- a decoder circuit, configured to:
- receive a first input;
- receive a second input;
- generate, based on the first input, a first decoded payload, the first decoded payload comprising a first data of a first length and a first flip bit, wherein the first flip bit indicates a bitwise polarity of the first data;
- and
- generate, based on the second input, a second decoded payload, the second decoded payload comprising a second data of a second length and a second flip bit, wherein the first length is less than the second length.
A method, comprising:
- receiving, at a processor circuit, a first input;
- generating, at the processor circuit and based on the first input, first syndrome coefficients and a first decoded payload based on the first syndrome coefficients, the first decoded payload comprising a first data of a first length and a first flip bit,
- receiving, at the processor circuit, a second input;
- and
- generating, at the processor circuit and based on the second input, a second decoded payload, the second decoded payload comprising a second data of a second length and a second flip bit, wherein the first length is less than the second length.
Dependencies are inferred from the claim text.