Random analog-to-digital converter compute cycle management for an analog in-memory computation processing system

A circuit, comprising:

• a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, each row including at least one word line connected to memory cells in the row, and each column including at least one bit line connected to memory cells in the column;
• wherein the memory cells store computational weight data for an in-memory computation operation;
• a word line driver circuit for each row having an output configured to drive the word line of the row;
• a row decoder circuit configured to actuate a plurality of the word line driver circuits in response to feature data of the in-memory computation operation;
• analog-to-digital converter circuitry configured, during a converter computation cycle, to convert analog signals generated on the bit lines of the columns to digital signals;
• and
• digital computation circuitry configured for processing the digital signals from the analog-to digital converter circuitry;
• and
• a control circuit configured to generate a randomization signal that is input to the analog-to-digital converter circuitry to control application of a randomized variation to the converter computation cycle;
• and
• wherein the digital computation circuitry also receives the randomization signal and the processing of the digital signals comprises adjusting the digital signals to remove error introduced by the random variation applied to the converter computation cycle of the analog-to-digital converter circuitry.