High bandwidth level-shifting differential analog interface circuit
AssigneeMicrochip Technology Incorporated
InventorMichael Alan Baxter
Life of this patent
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Abstract
Disclosed herein are apparatus, system, method, and computer-readable medium aspects for interfacing a MIPI transmitter with a SERDES receiver. An example method aspect includes receiving first and second MIPI signals at respective inputs and level-shifting each signal using corresponding diodes. The level-shifted signals are applied to the base terminals of first and second transistors, whose emitters are coupled together. A control current is generated via a current mirror formed by a third and fourth transistor, with the current set by a control voltage. This control current is supplied to the coupled emitters, enabling the production of differential output signals at the collector terminals of the first and second transistors for input to a SERDES receiver.
Claims20
An interface circuit, the interface circuit comprising:
- a first transistor having a base terminal, an emitter terminal, and a collector terminal;
- a second transistor having a base terminal, an emitter terminal, and a collector terminal, wherein the emitter terminal of the first transistor is coupled to the emitter terminal of the second transistor;
- a first diode having a cathode configured to be coupled to a first input, and an anode coupled to the base terminal of the first transistor;
- a second diode having a cathode configured to be coupled to a second input, and an anode coupled to the base terminal of the second transistor;
- and
- a third transistor and a fourth transistor coupled together to form a current mirror;
- wherein a collector terminal of the fourth transistor is coupled to the emitter terminals of the first and second transistors, and wherein a collector terminal of the third transistor is coupled to a control voltage;
- wherein the collector terminals of the first and second transistors are configured to provide differential output signals.
A method for interfacing a MIPI transmitter with a SERDES receiver, comprising:
- receiving a first MIPI signal at a first input and a second MIPI signal at a second input;
- level-shifting the first signal using a first diode and the second signal using a second diode;
- applying the level-shifted first and second signals to respective base terminals of a first transistor and a second transistor, wherein emitters of the first transistor and the second transistor are coupled together;
- generating a control current using a current mirror formed by a third transistor and a fourth transistor, wherein the control current is set by a control voltage;
- supplying the control current to the coupled emitters of the first transistor and the second transistor;
- and
- producing differential output signals at respective collector terminals of the first transistor and the second transistor for input to a SERDES receiver.
An interface circuit, the interface circuit comprising:
- a first transistor and a second transistor configured as a differential pair;
- and
- a current mirror comprising a third transistor and a fourth transistor,
- wherein a collector terminal of the fourth transistor is coupled to emitters of the first transistor and the second transistor, wherein a collector terminal of the third transistor is coupled to a control voltage, and wherein collector terminals of the first transistor and the second transistor are configured to provide differential output signals.
Dependencies are inferred from the claim text.