Flip-flops for a low power integrated circuit (ic)

A flip-flop with scan functionality for a low power integrated circuit (IC), the flip-flop with scan functionality comprising:

• a master stage flip-flop;
• a slave stage flip-flop;
• and
• a transistor bridge circuit for sharing a clock signal between the master stage flip-flop and the slave stage flip-flop;
• wherein the master stage flip-flop is further configured to generate a scan buffered output at a low phase of the clock signal based on a scan input and scan enable signals received at an input port of a multiplexer circuit at an input side of the master stage flip-flop, wherein a master stage internal feedback within the master stage flip-flop is provided by the scan buffered output, scan buffered inverted data and a high phase of the clock signal through a pull down network;
• and
• wherein the slave stage flip-flop is configured to generate a final output using the generated scan buffered output from the master stage flip-flop, wherein the generated scan buffered output controls the state of a cross-coupled inverters connected to the transistor bridge circuit in the slave stage flip-flop, and a slave stage internal feedback within the slave stage flip-flop is provided by the scan buffered data output and, scan buffered inverted data along with the low phase of the clock signal using the transistor bridge.

A reset flip-flop with scan functionality for a low power integrated circuit (IC), the reset flip-flop comprising:

• a master stage flip-flop;
• a slave stage flip-flop;
• and
• a transistor bridge circuit for sharing a clock signal between the master stage flip-flop and the slave stage flip-flop;
• wherein the master stage flip-flop is configured to receive an asynchronous reset input to the master stage flip-flop at an input port thereof and, wherein a final output thereof is reset to zero when a reset signal is turned high asynchronously;
• wherein the master stage flip-flop is further configured to generate a scan buffered output at a low phase of the clock based on a scan input and scan enable signals received at an input port of a multiplexer circuit at an input side of the master stage flip-flop,
• wherein master stage internal feedback within the master stage flip-flop is provided by the scan buffered output and, scan buffered inverted data along with a high phase of the clock signal through a pull-down network;
• wherein the slave stage flip-flop is configured to generate a final output using the generated scan buffered output from the master stage flip-flop and the state of the asynchronous reset signal, wherein the output of the master stage flip-flop and reset signal controls the state of cross-coupled NOR-inverter circuit connected to the transistor bridge circuit in the slave stage flip-flop and further controls the final output, and
• wherein a slave stage internal feedback within the slave stage flip-flop is provided by the scan buffered data output and, scan buffered inverted data along with the low phase of the clock signal using the transistor bridge circuit in a pull up network.