Resistive random-access memory structure and method

A structure comprising:

• an array of bit cells in columns and rows;
• source lines and bit lines for the columns, wherein each bit cell includes a programmable resistor and an N-type field effect transistor connected in series between a source line-bit line pair for a corresponding column;
• and
• a bit line biasing circuit connected to the bit lines,
• wherein the bit line biasing circuit is configured to apply specific bit line voltages to the bit lines to perform a memory operation in a bit cell in a selected column and a selected row, and
• wherein, when the memory operation is a write operation of multiple possible write operations, the bit line biasing circuit applies a positive unselected bit line voltage to all bit lines for all unselected columns.

A structure comprising:

• columns and rows of bit cells;
• source lines and bit lines for the columns, wherein each bit cell includes a programmable resistor and a P-type field effect transistor connected in series between a source line-bit line pair for a corresponding column;
• a bit line biasing circuit connected to the bit lines
• wherein the bit line biasing circuit is configured to apply specific bit line voltages to the bit lines to perform a memory operation in a bit cell in a selected column and a selected row, and
• wherein, when the memory operation is a write operation of multiple possible write operations, the bit line biasing circuit applies a positive unselected bit line voltage to all bit lines for all unselected columns;
• and
• a source line biasing circuit connected to the source lines,
• wherein the source line biasing circuit is configured to apply specific source line voltages to the source lines to perform the memory operation, and
• wherein, when the memory operation is the write operation, the source line biasing circuit applies a positive unselected source line voltage to all source lines for the unselected columns.