Clock delay compensation circuit and memory device including the same

A clock delay compensation circuit comprising:

• a four-phase clock generating circuit configured to generate a first phase clock signal, a second phase clock signal having a phase difference of 90 degrees from the first phase clock signal, a third phase clock signal having a phase difference of 180 degrees from the first phase clock signal, and a fourth phase clock signal having a phase difference of 270 degrees from the first phase clock signal using a differential clock signal pair,
• wherein the four-phase clock generating circuit comprises:
• a first circuit comprising a first inverter and a second inverter among a plurality of inverters connected in series;
• a second circuit in comprising a third inverter and a fourth inverter among the plurality of inverters connected in series;
• and
• a plurality of cross-coupled latches,
• wherein an output terminal of the fourth inverter is connected to an input terminal of the first inverter,
• wherein an output terminal of the second inverter is connected to an input terminal of the third inverter,
• wherein one of the plurality of cross-coupled latches connects an output terminal of the first inverter and an output terminal of the third inverter or connects the output terminal of the second inverter and the output terminal of the fourth inverter;
• and
• wherein a first cross-coupled latch, being at least one of the plurality of cross-coupled latches, is configured to receive an external power supply voltage.

A memory device comprising:

• a memory cell array comprising a plurality of memory cells;
• a memory peripheral portion configured to control the memory cell array;
• and
• an interface comprising a system clock signal receiver, a data clock signal receiver, a data signal receiver, and a clock delay compensation circuit,
• wherein the clock delay compensation circuit comprises a four-phase clock generating circuit and a clock driver comprising a plurality of cross-coupled latches,
• wherein the clock driver is configured to generate a second differential clock signal pair using a first differential clock signal pair,
• wherein the four-phase clock generating circuit is configured to generate a first phase clock signal, a second phase clock signal having a phase difference of 90 degrees with respect to the first phase clock signal, a third phase clock signal having a phase difference of 180 degrees with respect to the first phase clock signal, and a fourth phase clock signal having a phase difference of 270 degrees with respect to the first phase clock signal using the second differential clock signal pair, and
• wherein a first cross-coupled latch, being at least one of the plurality of cross-coupled latches, is configured to receive an external power supply voltage.