Memory performing computing operation
AssigneeSK hynix Inc.
InventorsDong Hwan JIN, Seok Joon KANG, Jun Ho CHEON, Sang Hoon JEONG, Chang Won JEONG
Life of this patent
Estimating the term…
Abstract
A memory includes a bit line, first to Nth cell groups (N≥2), each with multiple memory cells connected to the bit line, and first to Nth current supply circuits supplying currents to the bit line. The first current supply circuit's current is determined by sensing the bit line current when input voltages are supplied to the first cell group. A kth current supply circuit's current (2≤k≤N) is determined by sensing the bit line current when input voltages are supplied to the first to kth cell groups, with the first to k−1th current supply circuits activated.
Claims18
A memory comprising:
- a bit line;
- first to Nth cell groups, each cell group comprising a plurality of memory cells connected to the bit line, where N is an integer of 2 or more;
- and
- first to Nth current supply circuits configured to supply currents to the bit line,
- wherein a current amount of the first current supply circuit is determined based on a result of sensing the current flowing through the bit line in a state in which input voltages are supplied to the memory cells of the first cell group, and
- a current amount of a kth current supply circuit is determined based on a result of sensing the current flowing through the bit line in a state in which input voltages are supplied to the memory cells of the first to kth cell groups and the first to k−1th current supply circuits are activated, where k is an arbitrary integer ranging from 2 to N.
An operating method of a memory, the operating method comprising:
- applying first input voltages to memory cells of a first cell group connected to a bit line;
- generating a first coarse code by performing a coarse analog-to-digital conversion on a current flowing through the bit line by the memory cells of the first cell group;
- supplying the bit line with a first current corresponding to the first coarse code;
- applying second input voltages to memory cells of a second cell group connected to the bit line;
- generating a second coarse code by performing a coarse analog-to-digital conversion on a current flowing through the bit line by the memory cells of the first cell group, the memory cells of the second cell group, and the first current;
- and
- supplying the bit line with a second current corresponding to the second coarse code.
A memory comprising:
- memory cells of a first cell group connected to a bit line;
- a first current supply circuit configured to supply a first current to the bit line to compensate for a current that the memory cells of the first cell group sink from the bit line;
- memory cells of a second cell group connected to the bit line;
- and
- a second current supply circuit configured to supply a second current to the bit line to compensate for a current that the memory cells of the second cell group sink from the bit line.
Dependencies are inferred from the claim text.