Semiconductor storage device comprising a replica bit line circuit

A semiconductor storage device, comprising:

• a memory cell array including a plurality of memory cells, each of the plurality of memory cells being connected to a corresponding bit line pair;
• a replica bit line circuit including a plurality of replica memory cells, each of the plurality of replica memory cells outputting a replica bit line signal to a common replica bit line in response to a replica word line signal;
• a sense amplifier circuit for amplifying a signal on the bit line pair in response to a sense amplifier startup signal generated based on the replica bit line signal;
• a write circuit having a function of giving a low potential to one bit line of the bit line pair connected to the memory cell of a write target, and bringing the low potential-side bit line to a negative potential in response to a negative potential boost signal;
• and
• a negative potential boost signal generation circuit for generating the negative potential boost signal, the replica bit line and a buffer circuit being included in a signal generation route of the negative potential boost signal, the buffer circuit being connected to the replica bit line and outputting the negative potential boost signal,
• wherein
• the buffer circuit includes a replica circuit of a write driver for outputting a control signal at a time of data write into the memory cell,
• at a time of data read from the memory cell, the replica bit line signal is output to the replica bit line in response to the replica word line signal, and the sense amplifier circuit is driven by a change of the sense amplifier startup signal in response to the replica bit line signal, and
• at a time of data write into the memory cell, the low potential-side bit line of the bit line pair of a write target is brought to a negative potential in response to the negative potential boost signal output from the negative potential boost signal generation circuit.