Customizable chip for ai applications
AssigneeApple Inc.
InventorsSaman NADERIPARIZI, Mohammad RASTEGARI, Sayyed Karen KHATAMIFARD
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Abstract
In one embodiment, a computing device includes an input sensor providing an input data; a programmable logic device (PLD) implementing a convolutional neural network (CNN), wherein: each compute block of the PLD corresponds to one of a multiple of convolutional layers of the CNN, each compute block of the PLD is placed in proximity to at least two memory blocks, a first one of the memory blocks serves as a buffer for the corresponding layer of the CNN, and a second one of the memory blocks stores model-specific parameters for the corresponding layer of the CNN.
Claims21
1-20. (canceled)
A semiconductor device comprising:
- an application-specific integrated circuit (ASIC) implementing a neural network, wherein:
- each of a plurality of logical units of the ASIC corresponds to one of a plurality of layers of the neural network;
- and
- at least one of the logical units corresponds to a convolutional layer of the plurality of layers and comprises a compute block and at least two memory blocks, wherein:
- the compute block is positioned in the ASIC in proximity to the at least two memory blocks relative to at least one other memory block of the ASIC;
- a first one of the at least two memory blocks serves as a buffer for the convolutional layer;
- and
- a second one of the at least two memory blocks stores model-specific parameters for the convolutional layer.
A semiconductor device comprising:
- an application-specific integrated circuit (ASIC) implementing a neural network, the ASIC comprising a plurality of compute blocks, wherein:
- a logical unit of the ASIC corresponds to a convolutional layer of a plurality of layers of the ASIC and comprises a compute block of the plurality of compute blocks and at least two memory blocks, wherein:
- the compute block is positioned in the ASIC in proximity to the at least two memory blocks relative to at least one other memory block and at least one other compute block of the plurality of compute blocks of the ASIC.
A semiconductor device comprising:
- an application-specific integrated circuit (ASIC) comprising a plurality of logical units, each logical unit corresponding to a respective layer of a subset of layers of a neural network identified as exceeding a threshold energy consumption when executed on a processor, wherein the ASIC is configured to:
- receive, from the processor, an input corresponding to an output of a preceding layer of the neural network and provide the input to a first logical unit of the subset;
- and
- provide to the processor an output generated by a last logical unit of the subset.
Dependencies are inferred from the claim text.