US 2026/0140735 A1Published application

Read only memory (rom) patching

AssigneeNXP B.V.

InventorsArtur Folwarczny, Filippo Cioni, Aaron Kelly

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Abstract

A read-only memory (ROM) receives an instruction address from a requestor and provides a fetched instruction from the instruction address. A ROM patcher includes storage circuitry to store a bank of entries, each entry having a corresponding bank address and is configurable as either a patch address entry or a patch replacement entry. A first entry of the bank is configured as a first patch address entry storing address information indicating a first range of ROM addresses for a first patch of instructions. A plurality of entries of the bank following the first entry are configured as a plurality of patch replacement entries, each storing a replacement instruction of the first patch. Control circuitry determines if the instruction address hits in the bank, and when it does, the replacement instruction from one of the plurality of patch replacement entries is returned to the requestor in place of the fetched instruction.

Claims20

Dependent claims

A data processing system, comprising:

a read-only memory (ROM) configured to receive an instruction address from a requestor of the data processing system and provide a fetched instruction from the instruction address of the ROM;
and
a ROM patcher comprising:
storage circuitry configured to store a bank of entries, each entry having a corresponding bank address and is configurable as either a patch address entry or a patch replacement entry, wherein a first entry of the bank is configured as a first patch address entry storing address information indicating a first range of ROM addresses for a first patch of instructions and a plurality of entries of the bank following the first entry are configured as a plurality of patch replacement entries, each storing a replacement instruction of the first patch, and
control circuitry configured to determine if the instruction address hits in the bank of entries, wherein, when the instruction address hits the address information of the first patch address entry, the replacement instruction from one of the plurality of patch replacement entries is returned to the requestor in place of the fetched instruction.

2 more elements

A data processing system, comprising:

a read-only memory (ROM) configured to receive an instruction address from a requestor of the data processing system and provide a fetched instruction from the instruction address of the ROM;
and
a ROM patcher comprising:
storage circuitry configured to store a bank of entries, each entry having a corresponding bank address, and a configuration entry configured to store a configuration indicator for each entry of the bank to indicate whether the entry is configured as a patch address entry or a patch instruction entry, wherein:
each patch address entry of the bank is configured to store address information which indicates a range of patchable ROM addresses for a corresponding instruction patch, and
each patch address entry of the bank has a set of one or more corresponding patch instruction entries in the bank, each configured to store a corresponding replacement instruction of the corresponding instruction patch, and
control circuitry configured to determine if the instruction address hits in the bank of entries by comparing the instruction address to each patch address entry of the bank, and when a hit occurs to a hit entry which is a patch address entry having at least two corresponding patch instruction entries, selecting one of the at least two corresponding patch instruction entries to return the corresponding replacement instruction in place of the fetched instruction to the requestor.

4 more elements

Dependencies are inferred from the claim text.