System and method for testing identical cores
AssigneeNXP B.V.
InventorsTarun Kumar Goyal, Abhishek Mahajan, Dishank Paragkumar Dalal
Life of this patent
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Abstract
An integrated circuit for facilitating testing of identical cores is provided. The IC includes identical cores and a diagnostic circuit for testing the identical cores. The diagnostic circuit receives test outputs that are generated by the identical cores based on test inputs. The diagnostic circuit identifies defective identical cores from the identical cores based on the test outputs and a default output. The diagnostic circuit further outputs defective outputs associated with defective identical cores. The defective outputs are provided to a test system as failure logs of the defective identical cores.
Claims20
An integrated circuit (IC), comprising:
- a plurality of cores that are identical, wherein each core of the plurality of cores is configured to generate a respective test output based on a plurality of test patterns;
- and
- a diagnostic circuit coupled to the plurality of cores, wherein the diagnostic circuit is configured to:
- receive (i) a plurality of test outputs that include the test output of each of the plurality of cores and (ii) a default selection signal, wherein the default selection signal indicates one of the plurality of test outputs as a default test output;
- identify, based on the plurality of test outputs and the default test output, a defective set of cores of the plurality of cores;
- and
- output a set of defective outputs associated with the defective set of defective cores as a set of failure logs.
A diagnostic method, comprising:
- generating, by each core of a plurality of cores of an integrated circuit (IC), a respective test output based on a plurality of test patterns, wherein the plurality of cores are identical;
- receiving, by a diagnostic circuit of the IC, (i) a plurality of test outputs that include the test output of each of the plurality of cores and (ii) a default selection signal, wherein the default selection signal indicates one of the plurality of test outputs as a default test output;
- identifying, by the diagnostic circuit, based on the plurality of test outputs and the default test output, a defective set of cores of the plurality of cores;
- and
- outputting, by the diagnostic circuit, a set of defective outputs associated with the defective set of cores as a set of failure logs.
Dependencies are inferred from the claim text.