Semiconductor package for stress isolation

A semiconductor package, comprising:

• a substrate having multiple conductive layers coupled to bond pads at a surface of the substrate;
• a semiconductor die including a device side facing the substrate, the device side having first and second circuitry regions, the first circuitry region having greater sensitivity to at least one of mechanical or thermal stress than the second circuitry region and circumscribing the second circuitry region;
• conductive members coupled to the bond pads of the substrate, in direct physical contact with the second circuitry region, and not in direct physical contact with the first circuity region;
• a first ring on the substrate and encircling the bond pads;
• a second ring on the substrate and encircling the first ring;
• a glob top member covering the semiconductor die and an area of the substrate defined by the second ring;
• a mold compound covering the glob top member and the substrate.

A method for manufacturing a semiconductor package, comprising:

• forming a substrate including:
• a first conductive layer;
• a second conductive layer positioned below the first conductive layer;
• a via coupled between the first and second conductive layers;
• a dielectric covering the first and second conductive layers and the via;
• and
• a first support member at a top surface of the substrate;
• coupling conductive members on a device side of a semiconductor die to bond pads on the substrate, the device side of the semiconductor die including first and second circuitry regions, the first circuitry region having greater sensitivity to at least one of mechanical or thermal stress than the second circuitry region, the conductive members in direct physical contact with the second circuitry region and not in direct physical contact with the first circuitry region, a second support member on the device side vertically aligned with the first support member;
• underfilling a volume between the substrate and the device side with a first glob top member;
• covering the semiconductor die and the substrate with a second glob top member, the substrate including a ring to restrict flow of the second glob top member;
• and
• covering the second glob top member and the substrate with a mold compound.